The present invention relates to methods of forming integrated circuit devices, and more particularly to methods of forming integrated circuit capacitors.
The demand for higher capacity semiconductor memory devices has resulted in improved techniques to form memory devices and structures therein at higher levels of integration. However, because higher levels of integration typically require memory devices having smaller unit cell size, the area occupied by a cell capacitor in a memory device, such as a DRAM device, may have to be reduced significantly. As will be understood by those skilled in the art, this reduction in cell capacitor area can degrade memory cell performance if concomitant reductions in cell capacitance also occur.
Conventional methods of increasing cell capacitance include the use of thinner dielectric layers, high dielectric strength material and three-dimensional capacitor electrode structures. Conventional methods of increasing cell capacitor area also include forming cell capacitor electrodes (e.g., storage electrodes) with hemispherical grain (HSG) silicon surface layers. For example, a conventional method of forming HSG silicon surface layers on cell capacitor electrodes is disclosed in U.S. Pat. No. 5,407,534 to Thakur. The basic structure of an HSG capacitor is also disclosed in U.S. Pat. No. 5,597,756 to Fazan et al. However, while capacitors having HSG surface layers therein (hereinafter xe2x80x9cHSG capacitorsxe2x80x9d) have manifested enhanced capacitance in high density integrated circuits, HSG capacitors may lack stability and may incur performance degradation over the lifetime of an integrated circuit memory device when formed using conventional methods.
Such conventional methods of forming HSG capacitor electrodes may include the use of amorphous silicon and silane gas as a seed gas, with silicon atom migration taking place in a vacuum atmosphere. Alternatively, impurity doped amorphous silicon layers may be used to form HSGs without requiring seeding. As will be understood by those skilled in the art, the silicon atom migration rate during HSG formation may vary depending on the seeding time, the seed gas flow rate and temperature and pressure. The level of impurity doping concentration in amorphous silicon layers may also determine the size, quantity and rate at which HSGs form from amorphous silicon layers.
Referring now to FIGS. 1-3, conventional methods of forming HSG capacitors will be described. As illustrated by FIG. 1, a conventional method of forming an HSG capacitor may include the steps of forming a plurality of conductive plugs 20 on a substrate containing an electrically insulating layer 10 thereon. A plurality of amorphous silicon patterns 30 may also be formed on respective conductive plugs 20, as illustrated. Conventional HSG formation techniques are used to increase the surface area of the amorphous silicon patterns 30 by forming HSGs thereon. A dielectric layer 40 and upper capacitor electrode 50 are then formed to complete the integrated circuit capacitor structure. As illustrated by FIG. 2, the surface area of each lower capacitor electrode may be increased by forming U-shaped amorphous silicon patterns 32 as three-dimensional electrodes. However, while such U-shaped amorphous silicon patterns 32 may have increased surface area for a given lateral xe2x80x9cfootprintxe2x80x9d or cell size, the formation of HSGs on the outer sidewalls of the U-shaped patterns 32 may increase the likelihood of reliability failures if HSGs on adjacent patterns 32 become electrically connected to each other by silicon xe2x80x9cbridgesxe2x80x9d that may form during the HSG formation steps. In addition, the formation of HSGs typically causes migration of silicon atoms within the U-shaped patterns 32 and such migration, if excessive, may result in an undesirable and nonuniform thinning of the U-shaped patterns 32. Such thinning may make the U-shaped patterns 32 more susceptible to fracture and breakage during subsequent process steps. To address these limitations associated with the capacitors of FIG. 2, steps may taken to mask the outer sidewalls of each U-shaped pattern during HSG formation. Thus, as illustrated by FIG. 3, conventional methods may include the steps of forming HSGs only on the enclosed upper surfaces of the U-shaped patterns 34.
Notwithstanding these conventional techniques, improved methods of forming HSG capacitors are still needed to address limitations associated with conventional methods.
It is therefore an object of the present invention to provide improved methods of forming integrated circuit capacitors and capacitors formed thereby.
It is another object of the present invention to provide methods of forming integrated circuit capacitors having high capacitance values and capacitors formed thereby.
It is still another object of the present invention to provide methods of forming integrated circuit capacitors having uniform capacitance characteristics across an integrated circuit substrate and capacitors formed thereby.
It is a further object of the present invention to provide methods of forming integrated circuit capacitors having highly uniform capacitance characteristics when reversed and forward biased and capacitors formed thereby.
It is still another object of the present invention to provide methods of forming integrated circuits having capacitors therein with improved long-term reliability.
These and other objects, advantages and features of the present invention are provided by methods of forming integrated circuit capacitors that include the steps of forming a first capacitor electrode (e.g., lower electrode) containing hemispherical grains (HSGs) of silicon from an amorphous silicon layer having a nonuniform doping profile therein. According to a preferred aspect of the present invention, the nonuniform doping profile in the amorphous silicon layer includes a high-to-low doping gradient in a direction extending towards an upper surface thereof. Steps are then performed to form a dielectric layer on the first capacitor electrode and form a second capacitor electrode on the dielectric layer, opposite the first capacitor electrode.
The high-to-low doping gradient in the amorphous silicon layer is preferably achieved by forming the amorphous silicon layer as a composite of a plurality of amorphous silicon layers having different concentrations of dopants therein which may be added using in-situ doping techniques. For example, the first capacitor electrode may be formed by depositing a lower amorphous silicon layer having a relatively high doping concentration therein on a substrate and then depositing an upper amorphous silicon layer having a relatively low doping concentration therein on the lower amorphous silicon layer. Because of the lower doping concentration in the upper amorphous silicon layer (relative to the lower amorphous silicon layer), steps to convert the upper amorphous silicon layer into an HSG layer will result in the formation of an HSG layer with relatively large silicon grains and potentially uneven thickness. However, because silicon atom migration is suppressed in the relatively highly doped amorphous silicon layer, the conversion steps may not contribute significantly to the migration of silicon atoms from the lower more highly doped amorphous silicon layer. Thus, the lower amorphous silicon layer will remain essentially intact during the conversion steps with only relatively small HSGs being formed thereon. More uniform capacitance can therefore be achieved (across a substrate and from wafer-to-wafer) by increasing the uniformity of the thicknesses of the resulting HSG lower capacitor electrodes. Increased reliability can also be achieved by reducing the likelihood of xe2x80x9cbridgingxe2x80x9d between adjacent lower capacitor electrodes on a highly integrated substrate (i.e., between the HSGs on adjacent capacitors). This increased reliability is achieved by forming no HSGs or only relatively small HSGs on those portions of adjacent lower electrodes that are in closest proximity to each other, using preferred doping techniques which inhibit large HSG formation.
According to a preferred embodiment of the present invention, a method of forming an integrated circuit capacitor may comprise the steps of forming a substrate having a conductive plug (e.g., polysilicon plug) therein and forming a first electrically insulating layer on the substrate. The first electrically insulating layer is patterned to have an opening therein that exposes the conductive plug. Steps are also performed to form an amorphous silicon layer in the opening and in contact with the exposed conductive plug. The amorphous silicon layer preferably has a doping profile therein that includes a high-to-low doping gradient in a direction extending towards an upper surface thereof. The upper surface of the amorphous silicon layer is then converted into an HSG layer using HSG formation techniques that may include silicon nucleation and annealing steps. A dielectric layer and an upper capacitor electrode are then formed on the HSG layer.
According to a preferred aspect of this embodiment, the step of forming a dielectric layer is preceded by the step of planarizing the HSG layer to expose the first electrically insulating layer and the converting step comprises annealing the amorphous silicon layer. The planarizing step is also followed by the step of etching the first electrically insulating layer to expose a portion of the annealed amorphous silicon layer that does not contain hemispherical grains of silicon thereon. Alternatively, the converting step may be preceded by the steps of planarizing the amorphous silicon layer to expose the first electrically insulating layer and define a U-shaped amorphous silicon layer, and then etching the electrically insulating layer to expose sidewalls of the U-shaped amorphous silicon layer. Moreover, to achieve even higher capacitance per unit area, the converting step may comprise forming hemispherical grains of silicon on the exposed sidewalls of the U-shaped amorphous silicon layer so that the effective surface area of the first capacitor electrode is increased.
According to a further embodiment of the present invention, preferred HSG capacitors are provided that comprise a U-shaped lower electrode having inner and outer surfaces and hemispherical grains grown thereon. A dielectric film is also deposited on the U-shaped lower electrode and an upper electrode is formed on the dielectric film. According to a preferred aspect of this embodiment, the average size of the hemispherical grains formed on the inner surface of the U-shaped lower electrode may be larger than the average size of the hemispherical grains formed on the outer surface of the U-shaped lower electrode. In addition, an undercut may be formed at the base of the U-shaped lower electrode and the dielectric film and the upper electrode may be formed beneath the base of the lower electrode. Hemispherical grains may also be formed on the base of the lower electrode.
According to still another embodiment, an HSG capacitor is provided comprising a stacked lower electrode having a top surface and sides and hemispherical grains grown on the top surface and sides. A dielectric film is also deposited on the stacked lower electrode and an upper electrode is formed on the dielectric film. Here, the average size of the hemispherical grains formed on the sides of the stacked lower electrode is smaller than the average size of the hemispherical grains formed on the top surface of the stacked lower electrode. According to a further aspect of this embodiment, an undercut may be formed at the base of the U-shaped lower electrode and the dielectric film and the upper electrode may be formed beneath the base of the lower electrode. Hemispherical grains may also be formed on the base of the lower electrode.